An Error Correction Code (ECC)-enabled memory device is generally referred to a memory device that includes additional information, called ECC (Error Correction Code) bits (which are typically referred to as “parity bits”), stored in the memory device in addition to actual data bits. Such parity bits are used to check consistency of the data bits when the data bits are read from the memory device. In general, using the parity bits, corruption (e.g., errors) of data bits can be detected and the corrupted data bits can be corrected.
In such an ECC-enabled memory device, the parity bits are typically generated through an ECC engine to be associated with the corresponding data bits. For example, to detect or correct errors of a data word having N data bits, M bits of parity bits are generated to be associated with the N data bits. As such, the number of cells in the memory device that are used to store the N data bits is N+M bits. In response to a write access to the ECC-enabled memory device (i.e., writing a plurality of data bits to the memory device), corresponding parity bits will be computed and written to the memory device along with the plurality of data bits. When the plurality of data bits are read, consistency of data bits is checked using the corresponding parity bits, and any data error, if present, may be accordingly corrected.
In various applications, while updating the N data bits, instead of updating all N bits, there may be plural partial-write cycles, each of which is configured to update a corresponding subset of the N data bits, performed to update the whole N data bits. In an example where the above-mentioned data word has 64 data bits (N=64), there may be a total of 4 partial-write cycles performed to update the total of 64 data bits. Every time when the partial-write cycle is performed the update the corresponding subset of data bits, a corresponding set of parity bits are generated (e.g., updated). In accordance with the 4 partial-write cycles, the corresponding sets of parity bits are repeatedly written to same cells of the memory device, which disadvantageously impacts respective endurances of the cells that present the parity bits. Thus, existing techniques to perform partial-write cycles in the ECC-enabled memory device are not entirely satisfactory.